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Design for test of digital and anlog circuits (SEI-MT-S9) - 5PMECVT8

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  • Number of hours

    • Lectures : 14.0
    • Tutorials : 0
    • Laboratory works : 20.0
    • Projects : 0
    • Internship : 0
    ECTS : 3.5

Goals

The main objectives are to introduce the concept of Design for Testability for integrated circuits or in other words how to design produce and test a design where the number of faulty circuit is reduced and how to detect faulty devices.

Contact Mounir BENABDENBI

Content

•Fault Models (Stuck at and delay faults)
•ATPG and fault simulation
•Design For Testability (scan path, BIST, Boundary Scan-JTAG)
•Memory test – Test algorithmes (arch Test)
•Test techniques for mixed and analog circuits (for MT cursus only)
•RF and mixed systems Test (for MT cursus only)



Prerequisites

Basic digital circuits (logic gates and flip flops, registers, ...)

Tests



Additional Information

This course brings 2.0 ECTS to students in UE Advanced design (3A-AP)

Curriculum->ALTERNANCE MT->Semester 9
Curriculum->SEI->Semester 9

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Date of update October 5, 2017

Grenoble INP Institut d'ingénierie Univ. Grenoble Alpes