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Hardware Modeling and Synthesis - 4PMSMSM9

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  • Number of hours

    • Lectures : 12.0
    • Tutorials : 6.0
    • Laboratory works : 0
    • Projects : 0
    • Internship : 0
    ECTS : 2.0

Goals

  • Understanding the need of hardware modeling
  • Describing concepts of hardware modeling
  • Analyzing and understanding the HDL semantic for synthesis
  • Labwork : design and rapid prototyping
Contact Laurent FESQUET

Content

  • HDL and programming language
  • The abstraction levels
  • The synthesis
  • Definition of a synthesizable VHDL subset
  • The STD_LOGIC_1164 package
  • Modeling and synthesizing combinatory circuits
  • Modeling and synthesizing synchronous circuits
  • Relation between the VHDL semantic and the gate level description
  • Synthesis with constraints (area / timing)
  • Post-synthesis simulation
  • Place & Route
  • Back-annotation with the VITAL package
  • Post-routing simulation


Prerequisites

Tests

Written examination



Additional Information

Curriculum->Master TSI SIGMA->Semester 8
Curriculum->SICOM->Semester 8
Curriculum->Master->Semester 8

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Date of update January 9, 2017

Grenoble INP Institut d'ingénierie Univ. Grenoble Alpes