Phelma Formation 2022

Hardware Modeling and Synthesis - 4PMSMSM9

  • Number of hours

    • Lectures 12.0
    • Projects 0
    • Tutorials 6.0
    • Internship 0
    • Laboratory works 0

    ECTS

    ECTS 1.5

Goal(s)

  • Understanding the need of hardware modeling
  • Describing concepts of hardware modeling
  • Analyzing and understanding the HDL semantic for synthesis
  • Labwork : design and rapid prototyping
Contact Laurent FESQUET

Content(s)

  • HDL and programming language
  • The abstraction levels
  • The synthesis
  • Definition of a synthesizable VHDL subset
  • The STD_LOGIC_1164 package
  • Modeling and synthesizing combinatory circuits
  • Modeling and synthesizing synchronous circuits
  • Relation between the VHDL semantic and the gate level description
  • Synthesis with constraints (area / timing)
  • Post-synthesis simulation
  • Place & Route
  • Back-annotation with the VITAL package
  • Post-routing simulation


Prerequisites

Test

Written examination



Additional Information

Course list
Curriculum->Engineering degree->Semester 8