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Number of hours
Lectures : 3.0
Tutorials : 3.0
Laboratory works : 10.0
Projects : ?
Internship : ?
Written tests : ?
ECTS : 1.0
The objective of this module is to learn the description language VHDL/AMS and to be able to implement it in the frame of a mixed simulation project (including physical description and electronics) of an integrated sensor
4h of lecture to present the theory of VHDL/AMS description language 12h of practical work using the Cacence framework. This practical work is a project in which VHDL/AMS as well as VHDL and analog electronics are used to simulate a complete system
Notions of VHDL Notions of analog electronics design
the grade is given on a written report about the practical work