Number of hours
- Lectures 0
- Projects 0
- Tutorials 0
- Internship 0
- Laboratory works 24.0
- Written tests 0
ECTS
ECTS 2.0
Goal(s)
Put in practice all approaches from digital design and design flow
(Digital Design Lab Works)
Content(s)
VLSI Design (12h TP)
•Synthesis under constraints in ASIC approach
•Standard cell library presentation
•Floorplaning and Placement
•Clock tree
•Routing
Digital deign and prototyping (12h TP)
•Digital circuit modelling
•Simulation and properties verification
•Synthesis for FPGA purposes
•Place and route on FPGA
Prerequisites
Test
1/3CC+ 2/3 CR
Additional Information
Course list
Curriculum->Engineering degree->Semester 7