Number of hours
- Laboratory works 28.0
ECTS
ECTS 2.0
Goal(s)
this course introduces the new concepts of design and validation of HW/SW SOC (Codesign, Cosimulation, RTOS for SoC, exploration and performance estimation ...etc.)
Contact Andrea BATTISTELLA, Pierre-Yves MARTINEZContent(s)
SOC modeling and specification
Computational models (data-flow, process network, control-flow, ... , Functional models, TLM models, synthesis models in SystemC )
Design methodology of systems
HW/SW partitioning and co design
Co-simulation Platform based design and IP based design techniques
Modern RTOS design techniques
Protocols adapters generation
Architectural issues
Performances analysis
SW embedded design
The lab work applies to an example of image processing application in SystemC
Functional modelling, TLM, and RTL as well as co simulation
Prerequisites
1 mark on report