Number of hours
- Projects 32.0
ECTS
ECTS 3.0
Goal(s)
The objective of this project is to design the building blocks of a wireless front-end Wifi (2,4GHz) integrated in a process CMOS 0.35µm. The design of each block is based on the specifications from the system analysis previously made under the overall project.
Contact à préciser * ENSEIGNANTContent(s)
The content of the project includes the design of the following blocks:
A-receiver:
- Low Noise Amplifier + Mixer
- Gmc baseband Filter
B-module program: - Image rejection mixer
- Power amplifier
C-Frequency Synthesis - VCO + Buffer
- analog frequency predivider
- Phase frequency comparator and charge-pump
- digital frequency divider
Prerequisites
cours: analog integrated systems design for RF application
Test
Continuous assessment, written report and defence
Additional Information
Course list
Curriculum->Master->Semester 5
Curriculum->SEI->Semester 5
Curriculum->Double-Diploma Engineer/Master->Semester 5
Curriculum->Master EEA WICS->Semester 5