Number of hours
- Lectures 12.0
- Projects 0
- Tutorials 10.0
- Internship 0
- Laboratory works 0
ECTS
ECTS 2.0
Goal(s)
Understand basic and advanced digital design techniques, using different logic styles, and master optimization techniques from gate to circuit level.
Contact Regis LEVEUGLEContent(s)
Main characteristics of static CMOS logic
Logic styles : static, pass transistor and dynamic
Arithmetic functions
Latches, flip-flops
Memory blocks
Electrical optimization: transistor sizing, amplification techniques
Processor-like synchronous circuits based on control part and datapath
Prerequisites
Combinatorial and sequential logic
Test
2-hour written exam + continuous assessment
examen écrit (2h, avec documents) en session 1
Session 1 si confinement : examen écrit 1h ou QCM Chamilo selon possibilités
en session 2, rattrapage oral 30 minutes sans documents, remplaçant la note précédente - oral remplacé par un examen écrit si trop d'étudiants concernés
Session 2 si confinement : oral 30 minutes via zoom
Additional Information
Course list
Curriculum->Engineering degree->Semester 7