Number of hours
- Lectures 16.5
- Projects 0
- Tutorials 16.5
- Internship 0
- Laboratory works 0
ECTS
ECTS 2.5
Goal(s)
This course aims at presenting the advanced hardware mechanisms that are used for optimized program execution in computers.
These mechanisms allow to drastically increase processor and memory subsystem performance, and are also required to understand on chip or on board communication infrastructure. Other hardware mechanisms are necessary to understand more system related problems, such as parallel programming and virtual memory handling in operating systems.
Content(s)
*Bus infrastructure : notion of master, slave, arbiter
*RISC processor architecture study, based on the R3000
*Caches, design and policies
*Virtual memory support, TLB, MMU
*Multiprocessor SMP/MP, hardware support for cache coherency and memory consistency, locks engines
Prerequisites
Digital circuits and computer architecture elements and Assembly language programming Modules
Test
one written exam (3 h). If failed, a second 2h exam.
N1=E1
N2=E2
Additional Information
Course list
Curriculum->Engineering degree->Semester 8
Bibliography
David Patterson et John Hennessy, Computer Architecture, A Quantitative Approach, 4ème édition, Morgan Kaufman
William Stallings, Computer Organization and Architecture, 5ème édition, Prentice-Hall