Number of hours
- Lectures 0
- Projects 0
- Tutorials 0
- Internship 0
- Laboratory works 16.0
- Written tests 0
ECTS
ECTS 1.5
Goal(s)
Discover and practice the design techniques learned during the Harware Modeling and Synthesis lectures.
Design a digital FIR filter and implement it on a prototyping FPGA board.
Contact Laurent FESQUETContent(s)
- Simulation of VHDL codes
- Synthesis
- Place and Route
- Prototype on a FPGA board
Prerequisites
Test
Labwork report
Additional Information
Course list
Curriculum->Engineering degree->Semester 8