Number of hours
- Lectures 8.0
- Projects 0
- Tutorials 0
- Internship 0
- Laboratory works 20.0
ECTS
ECTS 2.0
Goal(s)
Provide both a global and accurate vision of a system behavior through a practical approach.
Understand issues and constraints when designing a complex system on a chip including one or many processors.
Content(s)
- Introduction: intégration aspects, rôle of components, standards, …
- Memory Hierarchy & Virtual memory:
- Types of memories: L1, L2, L3
- Caches, adressing space, segmentation, pagination, MMU & TLB
- System mono-processor running multiple tasks
- DMA
- Interruptions exceptions & traps management: code analysis
- Interruptions & context management: code analysis
- Multi-processors system running multiple tasks
- Basics on Buses and NoCs
- Shared Memory vs Message passing
- Synchronisation issues
- Memory Coherence and consistency
Lab (20h)
Contents:
- Study of a Motion JPEG application
- Codesign HW/SW of this application using SystemC programming language
- Partitionning HW/SW
- Mapping and simulating the application on a multi-processors virtual platform: study and performances optimizations
Prerequisites
Test
Exam and reports
CC (note basée sur les compte rendus de TPs)
Examen écrit Session1 : DS1
Examen écrit Session 2 : DS2
N1 = Note finale session 1
N2 = Note finale session 2
3A filière MT Calcul Note finale
N1 = 50% CC + 50% DS1
N2 = 50% CC + 50% DS2 (conservation de la note de CC de session1)
Additional Information
Course list
Curriculum->Alternance MT->Semester 9