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Our engineering & Master degrees
Our engineering & Master degrees

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Digital integrated system Labwork - 4PMEM3L1

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  • Number of hours

    • Lectures : 0
    • Tutorials : 0
    • Laboratory works : 24.0
    • Projects : 0
    • Internship : 0
    • Written tests : 0
    ECTS : 2.0

Goals

Put in practice all approaches from digital design and design flow
(Digital Design Lab Works)

Content

VLSI Design (12h TP)
•Synthesis under constraints in ASIC approach
•Standard cell library presentation
•Floorplaning and Placement
•Clock tree
•Routing

Digital deign and prototyping (12h TP)

•Digital circuit modelling
•Simulation and properties verification
•Synthesis for FPGA purposes
•Place and route on FPGA



Prerequisites

Tests



Additional Information

Curriculum->Engineering degree->Semester 7

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Université Grenoble Alpes