EU Digital Architecture - 4PUEANUM

Goal(s)

This course unit (UE) addresses two complementary optimization axes of integrated digital systems: confidence in ensuring proper service despite various threats, and computing power. For the first axis, the objective is to raise awareness of natural or intentional threats that can disrupt the proper functioning of systems, and of methods for countering or mitigating the impact of these threats at the hardware and embedded software levels. For the second axis, the objective is to understand the evolution of digital architectures aiming at increasing computing power, particularly the different processor architectures and their associated memory hierarchy.

Content(s)

General context
Dependability of digital systems: threats and design methods
Hardware security of digital systems: threats and design methods
Architecture evolution for computing power

Digital design, Architecture with FSM and operative part, Basic operation of microprocessors, typical instruction set (ISA), addressing modes ...

Test

Session 1: written exam 2h (60% of total grade), architecture proposal report (20% of total grade) and report with continuous control of practical work (20% of total grade)

Session 2: written exam 2h replacing the previous exam grade, report and practical work grades unchanged

Additional Information

This course brings 2.5 ECTS to students in Engineer APPRENTISSAGE MT 2Y

Bibliography

K01-HEN
J. Hennessy, D. Patterson, Computer architecture: a quantitative approach, Morgan Kaufmann, (2nd edition 1996 and 5th edition 2012)
K01-PAT
D. Patterson, J. Hennessy, Organisation et conception des ordinateurs : l'interface matériel/logiciel, Dunod, 1994 (version française)
K04-PAT
D. Patterson, J. Hennessy, Computer organization and design: the hardware/software interface – RISC-V edition, Morgan Kaufmann, 2018