EU Digital electronics - 3PUEELNU

Informations générales

  • Number of hours

    • Lectures 18.0
    • Projects 0
    • Tutorials 10.0
    • Internship 0
    • Laboratory works 20.0

    ECTS

    ECTS 4.0

Goal(s)

Part 1
Acquire the basic concepts of digital circuit design:

  • information representation,
  • combinational circuits
  • sequential circuits,
  • state machines,
  • design by separating the control part from the operational part.

Part 2

  • Understanding the need for hardware system modeling
  • Concepts that characterize a hardware description language
  • System Verilog semantics for synthesis
Contact Sylvain HUET

Content(s)

  • Part 1*
  • Representation of information in digital machines (natural/relative integers, real numbers, other encodings)
  • Combinational circuits (Boolean algebra, representation and simplification of Boolean functions, fundamental combinational circuits: multiplexers, arithmetic circuits, etc.)
  • Sequential circuits (general architecture, basic components and fundamental circuits: counters, shift registers, etc.)
  • Synchronous state machine (formalism, Moore and Mealy machines, synthesis)
  • Design by separating the operational part from the control part
  • Practical application in a lab session on circuit design and its implementation on an FPGA

Part 2

  • Introduction and rationale for hardware system modeling
  • Levels of abstraction in digital microelectronics
  • System Verilog language for hardware modeling
  • Definition of a subset of the System Verilog language that can be synthesized
  • Modeling and synthesis of combinational circuits
  • Modeling and synthesis of state machines
  • Implementation in BE


Prerequisites

Test

CC1 and CC2:

  • 1/6 of the CC grade for Part 1 in the form of a lab report
  • 5/6 of the CC grade for Part 2 in the form of
        * Multiple-choice questions
        * Continuous assessment (CC)
        * Practical work report
  • ET1 and ET2:
        * 2/3 of the ET mark on a written exam on part 1
        * 1/3 of the ET mark on a written exam on part 2
    All documents and PHELMA calculators are permitted


Additional Information

This course brings 3.0 ECTS to students in Engineer APPRENTISSAGE MT 1Y

Course list
Curriculum->1st year engineer PET->Semester 6
Curriculum->Alternance MT->Semester 6

Bibliography

Partie 1
1] Architectures Logicielles et Matérielles,P. Amblard and J.-C. Fernandez and F. Lagnier and F. Maraninchi and P. Sicard and Ph. Waille, Dunod, collection Sciences Sup.,2000.
[2] Electronique Numérique Intégrée, J.-. Danger and S.Guilley and P. Matherat and Y. Mathieu and L. Naviner and A. Polti and J. Provost , cours de l'ENST Paris
[3]Représentation et Synthèse des Systèmes Logiques, S.Pravossoudovitch, Ecole polytechnique Universitaire de Montpellier, 2006
[4] Bebop to the Boolean Boogie: An Unconventional Guide to Electronics Fundamentals, Components and Processes, C. Maxfield and P. Waddell, Butterworth-Heinemann, 2002