EU Processor and microcontroller architecture - 4PUIAPMC

Goal(s)

The objective of this course is to provide a detailed understanding of the relationship between hardware and software in embedded systems, enabling effective programming of applications deployed on FPGAs or microcontrollers.

Content(s)

The Lectures and Tutorials will focus on processor architecture and memory hierarchy, and will, among other things:

• provide an overview of the major processor families and their architectures
• explain the concepts of pipelining and branch prediction in a processor
• explain the memory hierarchy and its impact on system performance
• provide an overview of the types of microcontrollers (µC) and their applications.
  Examples in lectures and tutorials will be based on a processor with the RISC-V instruction set.

A series of lab sessions and a mini-project will complement the theoretical component with the practical application of the concepts covered previously.
The lab sessions will utilize the Rocket Chip hardware/software co-design and simulation platform developed at the University of Berkeley. This platform is used here to simulate software execution (C and assembly, without an OS, in bare-metal mode) on a system architecture centered around a Rocket processor (RISC-V). These lab sessions will, among other things, reinforce the following concepts and skills:

• cross-compilation, linking, and use of debugging tools (gdb)
• event handling (exceptions, interrupts, system calls) on a rudimentary OS
• implementation of interrupts for task switching on a single-processor architecture
• integration of a new dedicated peripheral (described in Verilog) into the hardware system and software control
• Impact of cache architecture choices on program performance; measurement of hit and miss rates
  
  As part of a mini-project, an image classification application based on the execution of a CNN (Convolutional Neural Network) will be deployed on an FPGA board. This demonstrator will allow students to implement and visually observe certain concepts covered in lectures and lab sessions on a physical device

• C programming (basics)
• Phelma 1A "Ordinateur et microprocessors" course

Test

Session 1:
1 mark on exam (60%)
1 mark on reports (40%)
Session 2:
1 mark on exam (60%)
The mark on reports is kept from session 1

Additional Information

Bibliography

Book: Computer Architecture, Edition 7, A Quantitative Approach, By John L. Hennessy, David A. Patterson and Christos Kozyrakis