Number of hours
- Lectures 0
- Projects 56.0
- Tutorials 0
- Internship 0
- Laboratory works 0
ECTS
ECTS 5.0
Goal(s)
Experiment the circuit digital design and practice design flow with standard cell libraries from algorithm to layout
Contact Katell MORIN ALLORY, Laurent FESQUETContent(s)
Content
Design of a digital bloc or system
From specification to layout
Prototyping on FPGA
Examples: Microprocessors (MIPS, ColdFire, 386 ...), Crypto-processors (DES, AES, RSA), NoCs, Communication circuits (IrDA, Ethernet, USB ...), video filters, asynchronous design on FPGA, MIDI synthesizers, IP Z-buffer ...
Prerequisites
Test
Oral session and report
Projet non rattrapable
Note = notre du rapport et de la soutenance
Additional Information
This course brings 3.0 ECTS to students in Miniprojects to be chosen
Course list
Curriculum->SEI->Semester 8