Phelma Formation 2022

Transaction level modeling of systems on chip - 5PMIMTS0

  • Number of hours

    • Lectures 14.0
    • Projects 0
    • Tutorials 0
    • Internship 0
    • Laboratory works 10.0
    • Written tests 0

    ECTS

    ECTS 3.0

Goal(s)

To cope with the complexity of the development of modern systems-on-chip, the industry utilizes abstractions such as transaction-level models.
These models are generally written with the help of SystemC.

In this course, the students will learn the principles of transaction-level modeling in SystemC.
The various abstraction levels at which a model may be written and the different ways to integrate embedded software in the models will also be discussed.

Contact Frederic PETROT

Content(s)

*Short introduction to C++
*Presentation of SystemC
*The TLM-2 library
*Modeling issues, faithfulness of TLM models.
*Integration of the embedded software in a TLM platform
*Lab works



Prerequisites

*Concepts of computer architecture
*Programming in C

A knowledge of C++ is appreciable.

Test

written exam + labs



N1=(E1 + TP)/2
N2=(E2 + TP)/2

Additional Information

Course list
Curriculum->Engineering degree->Semester 9

Bibliography

1. Frank Ghenassia, Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems, 1st ed. (Springer, 2005).