Number of hours
- Lectures 8.0
- Projects 0
- Tutorials 8.0
- Internship 0
- Laboratory works 0
ECTS
ECTS 2.0
Goal(s)
The aim of this lecture is to present the physics of advanced CMOS devices together with process integration elements and some state-of-art architectures.
Contact Irina IONICAContent(s)
Carrier transport in long and short channel
Electrostatic effects in short channel
Process integration
Advanced architectures (SOI, FinFET)
Prerequisites
Solid state physics
Semiconductor Physics
Semiconductor device physics
Microelectronics technology
Test
Semester 8 - The exam is given in english only 
In-class SESSION1:
Type of assessment: Supervised written exam + continuous assessment (homework) 10%
Duration: 2 hours
Modalities: All documents are forbidden. Only a formula document will be distributed with the subject for the exam.
Calculator: allowed
In-class SESSION2:
Same modalities as in session 1 for supervised written exam part. The continuous assessment remains the same as in session 1
Lockdown conditions, session 1: same as in-class, with the exam on-line and on-line supervision (zoom).
Lockdown conditions, session 2: same as in-class, with the exam on-line and on-line supervision (zoom).
session 1 condition normale : 90% DS + 10% CC
session 2 condition normale : 90% DS rattrapage + 10% CC de la session 1
session 1 condition confinement : mêmes qu’en présentiel
session 2 condition confinement : mêmes qu’en présentiel
Additional Information
Semester 8 - This course is given in english only
Course list
Curriculum->NANOTECH->Semester 8
Bibliography
Physique des semiconducteurs et des composants électronique - Henry Mathieu - Dunod
Fundamentals of carrier transport - Mark Lundstrom - Cambridge university press
Semiconductor devices physics and technology - Sze