Number of hours
- Lectures 12.0
- Projects 0
- Tutorials 12.0
- Internship 0
- Laboratory works 0
ECTS
ECTS 1.5
Goal(s)
Understand basic digital design techniques, using different logic styles, and master some optimization techniques from gate to circuit level.
Contact Regis LEVEUGLEContent(s)
Main characteristics of static CMOS logic
Logic styles : static, pass transistor and dynamic
Arithmetic functions
Latches, flip-flops
Memory blocks
Electrical optimization: transistor sizing, amplification techniques
Processor-like synchronous circuits based on control part and datapath
Prerequisites
Combinatorial and sequential logic
Test
2-hour written exam
examen 2h avec documents en session 1
rattrapage remplaçant la note précédente en session 2, oral 30 minutes sans documents
Si confinement :
examen 1h avec oral 20 minutes via Zoom en session 1
mêmes modalités en session 2 via Zoom
Additional Information
Course list
Curriculum->Alternance MT->Semester 6