Phelma Formation 2022

Design for test of digital and anlog circuits (SEI-MT-S9) - 5PMECVT8

  • Number of hours

    • Lectures 14.0
    • Projects 0
    • Tutorials 0
    • Internship 0
    • Laboratory works 24.0

    ECTS

    ECTS 3.5

Goal(s)

The main objectives are to introduce the concept of Design for Testability for integrated circuits or in other words how to design produce and test a design where the number of faulty circuit is reduced and how to detect faulty devices.

Contact Mounir BENABDENBI

Content(s)

•Fault Models (Stuck at and delay faults)
•ATPG and fault simulation
•Design For Testability (scan path, BIST, Boundary Scan-JTAG)
•Memory test – Test algorithmes (arch Test)
•Test techniques for mixed and analog circuits (for MT cursus only)
•RF and mixed systems Test (for MT cursus only)



Prerequisites

Basic digital circuits (logic gates and flip flops, registers, ...)

Test

Semester 9 - The exam may be taken in french or in english FR EN



Contrôle continue : CC (note basée sur les compte rendus de TP)
Examen écrit Session1 : DS1
Examen écrit Session 2 : DS2
N1 = Note finale session 1
N2 = Note finale session 2

3A filière SEI Calcul Note finale

N1 = 40% CC + 60% DS
N2 = 40% CC + 60% DS

3A filière MT Calcul Note finale
CC: note compte rendus de TPs numériques
DS1: note examen écrit partie numérique (Mounir Benabdenbi)
DS2: note examen écrit partie analog./RF (Salvador Mir)

N1 = 33% CC + 34% DS1 + 33% DS2
N2 = 33% CC + 34% DS1 + 33% DS2

Additional Information

This course brings 2.0 ECTS to students in UE Advanced design 2 (3A-AP)

Semester 9 - This course may be followed in french or in english  
Course list
Curriculum->Alternance MT->Semester 9
Curriculum->SEI->Semester 9