Phelma Formation 2022

Design for test of digital and anlog circuits (SEI-MT-S9) - 5PMECVT8

  • Number of hours

    • Lectures 14.0
    • Projects 0
    • Tutorials 0
    • Internship 0
    • Laboratory works 24.0


    ECTS 3.5


The main objectives are to introduce the concept of Design for Testability for integrated circuits or in other words how to design produce and test a design where the number of faulty circuit is reduced and how to detect faulty devices.

Contact Mounir BENABDENBI


•Fault Models (Stuck at and delay faults)
•ATPG and fault simulation
•Design For Testability (scan path, BIST, Boundary Scan-JTAG)
•Memory test – Test algorithmes (arch Test)
•Test techniques for mixed and analog circuits (for MT cursus only)
•RF and mixed systems Test (for MT cursus only)


Basic digital circuits (logic gates and flip flops, registers, ...)


voir Evaluation

Additional Information

This course brings 2.0 ECTS to students in UE Advanced design 2 (3A-AP)

Course list
Curriculum->Engineering degree->Semester 9
Curriculum->Alternance MT->Semester 9