Phelma Formation 2022

Digital electronics - 3PMEENU3

  • Number of hours

    • Lectures 12.0
    • Projects 0
    • Tutorials 10.0
    • Internship 0
    • Laboratory works 8.0

    ECTS

    ECTS 2.5

Goal(s)

This course provides the basic skills necessary for the design of digital circuits. The knowledge acquired will be useful for understanding the computers and microprocessors course given during the PET S6 and the pre-orientation courses dealing with the design of digital circuits: pre-orientation SEI, SEOC.

Contact Sylvain HUET

Content(s)

Courses/TD (Courses: 6x2 hours, TD: 5x2 hours, TES: 2 hours)

  • Representation of information in digital machines (natural/relative integers, reals, other encodings)
  • Combinatorial circuits (Boolean algebra, representation and simplification of Boolean functions, fundamental combinatorial circuits: mux, arithmetic circuits,... )
  • Sequential circuits (general architecture, basic components and fundamental circuits: counter, shift register,...)
  • Finite state machine (formalism, Moore and Mealy machines, synthesis)
  • Design by separation of the operating part from the control part

Lab (2x4 hours)
It takes place after the Courses/TD and allows to apply all the notions seen. It deals with the design of an asynchronous RS232 serial receiver and its implementation on an FPGA. A conception document and a Quartus project are provided. The aim is to:

  • to determine the missing elements of the operative part,
  • to specify the control part with a state machine and to make its synthesis,
  • to enter these various elements of the operating and control parts in a Quartus project to be completed and to make the progressive validation from test benches provided, sometimes to be completed,
  • to validate the implementation of the circuit on a DE1 FPGA board by using the development PC to send it information in asynchronous series.


Prerequisites

None

Test

  • 2 hours written exam
  • Lab report


Examen écrit Session 1 : DS1
Examen écrit Session 2 : DS2
Rapport TP : RTP (non rattrapable)
N1 = 80%DS1 20%RTP
N2 = 80%DS2 20%RTP

Additional Information

Course list
Curriculum->1Y Core Curriculum->Semester 5

Bibliography

[1] Architectures Logicielles et Matérielles,P. Amblard and J.-C. Fernandez and F. Lagnier and F. Maraninchi and P. Sicard and Ph. Waille, Dunod, collection Sciences Sup.,2000.
[2] Electronique Numérique Intégrée, J.-. Danger and S.Guilley and P. Matherat and Y. Mathieu and L. Naviner and A. Polti and J. Provost , cours de l'ENST Paris
[3]Représentation et Synthèse des Systèmes Logiques, S.Pravossoudovitch, Ecole polytechnique Universitaire de Montpellier, 2006
[4] Bebop to the Boolean Boogie: An Unconventional Guide to Electronics Fundamentals, Components and Processes, C. Maxfield and P. Waddell, Butterworth-Heinemann, 2002