Functional Verification Methodology - 5PMEMVE0
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Number of hours
- Lectures : 10.0
- Tutorials : 0
- Laboratory works : 14.0
- Projects : 0
- Internship : 0
ECTS : 2.5
Goals
This module including lessons and labs will prépare the engineer students to design reliable circuits through the usage of functional verification and validation
Contact Francois CERISIER,
Katell MORIN ALLORY
Content *Introduction to vérification: strategies of verification and SystemVerilog base syntax
*UVM sequences: Creating de random test sequences (example of a UART design)
*Checking & assertions: Validation of expectations (score boarding principles)
*Code coverage and functional coverage
*Verification of integration at system level
*Introduction to formal verification: Assertions and SVA
Prerequisites*VLSI design
*Hardware design and modélisation language such as VHDL or Verilog
*Numeric architecture design
Tests Exam + lab report(s)
50% CC+50% exam
Additional Information Curriculum->Engineering degree->Semester 9
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Date of update October 14, 2019