Functional Verification Methodology - 5PMEMVE0

Goal(s)

This module including lessons and labs will prépare the engineer students to design reliable circuits through the usage of functional verification and validation

Content(s)

*Introduction to vérification: strategies of verification and SystemVerilog base syntax
*UVM sequences: Creating de random test sequences (example of a UART design)
*Checking & assertions: Validation of expectations (score boarding principles)
*Code coverage and functional coverage
*Verification of integration at system level
*Introduction to formal verification: Assertions and SVA

*VLSI design
*Hardware design and modélisation language such as VHDL or Verilog
*Numeric architecture design