Number of hours
- Lectures 12.0
- Projects 0
- Tutorials 6.0
- Internship 0
- Laboratory works 0
ECTS
ECTS 1.5
Goal(s)
- Understanding the need of hardware modeling
- Describing concepts of hardware modeling
- Analyzing and understanding the HDL semantic for synthesis
- Labwork : design and rapid prototyping
Content(s)
- HDL and programming language
- The abstraction levels
- The synthesis
- Definition of a synthesizable VHDL subset
- The STD_LOGIC_1164 package
- Modeling and synthesizing combinatory circuits
- Modeling and synthesizing synchronous circuits
- Relation between the VHDL semantic and the gate level description
- Synthesis with constraints (area / timing)
- Post-synthesis simulation
- Place & Route
- Back-annotation with the VITAL package
- Post-routing simulation
Prerequisites
Test
Written examination
Examen écrit Sessions 1 et 2 :
Note = Note finale session 1
Si session 2
Note = Note finale session 2