Number of hours
- Lectures 0
- Projects 0
- Tutorials 0
- Internship 0
- Laboratory works 20.0
- Written tests 0
ECTS
ECTS 1.0
Goal(s)
Deepen knowledge of Digital Design by following a large-scale project from the initial specification to the final circuit.
Contact Ghislaine MAURY, Jonathan MIQUELContent(s)
The project is centered around a specific component representative of SEOC applications: a Finite Impulse Response (FIR) filter.
The first half of the project focuses on the Front-End: starting from a high-level specification and a provided VHDL codebase (representing the Operative Part), students will specify, implement, and validate a FSM capable of controlling the filter.
In the second half, the filter will go through various Back-End stages (verification, synthesis, and Place & Route) to produce a “mask set” that could be used to fabricate the actual circuit. If time and resources permit, FPGA-based prototyping will also be considered.
Prerequisites
Fundamentals of Integrated Digital Electronic Design (Course of S7)
Test
Compte Rendu du Projet, non rattrapable
Additional Information
Course list
Curriculum->SEOC->Semester 8