Number of hours
- Lectures 0
- Projects 0
- Tutorials 0
- Internship 0
- Laboratory works 8.0
- Written tests 0
ECTS
ECTS 0.5
Goal(s)
This lab illustrates the logic course (3PMELOG6). It consists in designing an asynchronous serial data receiver (RS-232) and implementing it on an FPGA.
Contact Sylvain HUETContent(s)
The specification of the circuit using a state machine with variables is given as as well as the interface between the operative and control parts. The operative part is partially given.
This lab consists in:
- determining the missing parts of the operative part,
- specifying the control part with a state machine,
- synthesizing this state machine,
- capturing these different elements of the operative and control parts in a Quartus project,
- progressively validating the system with the provided test benches,
- implementing the circuit on a DE1 FPGA board.
This lab takes place in 2 sessions of 4 hours.
Prerequisites
Logic course (3PMELOG6)
Session 1 :
- Report to be delivered at the end of the last lab session
- Mark: 100% session 1 report
Session 2 :
- none : not recoverable
Confined session 1:
- Homework
- Mark: 100% confined session 1 homework
Confined session 2:
- none : not recoverable
Cf. encadré évaluation de la description de l'enseignement
[1] Architectures Logicielles et Matérielles,P. Amblard and J.-C. Fernandez and F. Lagnier and F. Maraninchi and P. Sicard and Ph. Waille, Dunod, collection Sciences Sup.,2000.
[2] Electronique Numérique Intégrée, J.-. Danger and S.Guilley and P. Matherat and Y. Mathieu and L. Naviner and A. Polti and J. Provost , cours de l'ENST Paris
[3]Représentation et Synthèse des Systèmes Logiques, S.Pravossoudovitch, Ecole polytechnique Universitaire de Montpellier, 2006
[4] Bebop to the Boolean Boogie: An Unconventional Guide to Electronics Fundamentals, Components and Processes, C. Maxfield and P. Waddell, Butterworth-Heinemann, 2002