School of engineering in Physics, Applied Physics, Electronics & Materials
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This lab illustrates the logic course (3PMELOG6). It consists in designing an asynchronous serial data receiver (RS-232) and implementing it on an FPGA.
Contact Sylvain HUETThe specification of the circuit using a state machine with variables is given as as well as the interface between the operative and control parts. The operative part is partially given.
This lab consists in:
Logic course (3PMELOG6)
Session 1 :
Session 2 :
Confined session 1:
Confined session 2:
Cf. encadré évaluation de la description de l'enseignement
[1] Architectures Logicielles et Matérielles,P. Amblard and J.-C. Fernandez and F. Lagnier and F. Maraninchi and P. Sicard and Ph. Waille, Dunod, collection Sciences Sup.,2000.
[2] Electronique Numérique Intégrée, J.-. Danger and S.Guilley and P. Matherat and Y. Mathieu and L. Naviner and A. Polti and J. Provost , cours de l'ENST Paris
[3]Représentation et Synthèse des Systèmes Logiques, S.Pravossoudovitch, Ecole polytechnique Universitaire de Montpellier, 2006
[4] Bebop to the Boolean Boogie: An Unconventional Guide to Electronics Fundamentals, Components and Processes, C. Maxfield and P. Waddell, Butterworth-Heinemann, 2002
Date of update March 6, 2019