Number of hours
- Lectures 8.0
- Projects 32.0
- Tutorials 0
- Internship 0
- Laboratory works 0
ECTS
ECTS 3.0
Goal(s)
The objectives of these projects are:
- acquire competences in mixed system simulation and Verilog/AMS.
- apply existing knowlege on analog design and Verilog.
- develop MEMS-based circuits with technologies that can be applied in industry
Content(s)
Groups of 2 to 3 students work on a complex applied project containing a sensor, some analog electronics and an A/D converter and digital electronics. These project are simulation only, no fabrication is involved.
Prerequisites
Verilog
analog design
Test
1/3 note du cours (S. Mir) + 2/3 note de projet (L. Bastard)
Additional Information
Course list
Curriculum->Engineering degree->Semester 9
Bibliography
Y. Hervé, "VHDL-AMS, Applications et enjeux industriels", Dunod, 2002