Phelma Formation 2022

Modelling numerical circuits - 4PMEM3V1

  • Number of hours

    • Lectures 6.0
    • Projects 0
    • Tutorials 0
    • Internship 0
    • Laboratory works 12.0
    • Written tests 0

    ECTS

    ECTS 2.0

Goal(s)

Why hardware designs need to be modelled
Concept of Hardware description languages
System Verilog semantics for synthesis

Contact Katell MORIN ALLORY

Content(s)

•System Verilog and the programming language

•Abstraction levels

•Modelling and synthesis of combinatorial circuits

•Modelling and synthesis of finite state machine



Prerequisites

Test

QCM
Continuous evaluation
Lab report
FInal note: average of QCM, Continous evaluation and Lab report
IN case of confinement, the evaluation method will not change.



1/3 QCM+ 1/3 CC +1/3 CR

Additional Information

Course list
Curriculum->Engineering degree->Semester 7

Bibliography

VHDL du langage à la modélisation, R. Airiau J.-M. Bergé, V. Olive J. Rouillard, Presses Polytechniques et Universitaires Romandes