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Our engineering & Master degrees
Our engineering & Master degrees

> Studies

Modelling numerical circuits - 4PMEM3V1

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  • Number of hours

    • Lectures : 6.0
    • Tutorials : 0
    • Laboratory works : 12.0
    • Projects : 0
    • Internship : 0
    • Written tests : 0
    ECTS : 1.5

Goals

Why hardware designs need to be modelled
Concept of Hardware description languages
System Verilog semantics for synthesis

Contact Katell MORIN ALLORY

Content

•System Verilog and the programming language

•Abstraction levels

•Modelling and synthesis of combinatorial circuits

•Modelling and synthesis of finite state machine



Prerequisites

Tests

QCM
Continuous evaluation
Lab report
FInal note: average of QCM, Continous evaluation and Lab report
IN case of confinement, the evaluation method will not change.



1/3 QCM+ 1/3 CC +1/3 CR

Additional Information

Curriculum->Engineering degree->Semester 7

Bibliography

VHDL du langage à la modélisation, R. Airiau J.-M. Bergé, V. Olive J. Rouillard, Presses Polytechniques et Universitaires Romandes

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Université Grenoble Alpes