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Our engineering & Master degrees
Our engineering & Master degrees

> Studies

Modelling numerical circuits - 4PMEM3V1

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  • Number of hours

    • Lectures : 6.0
    • Tutorials : 0
    • Laboratory works : 12.0
    • Projects : 0
    • Internship : 0
    • Written tests : 0
    ECTS : 1.5

Goals

Why hardware designs need to be modelled
Concept of Hardware description languages
VHDL semantics for synthesis

Contact Lorena ANGHEL

Content

•VHDL and the programming language

•Abstraction levels

•Synthesizable VHDL subset
•Modelling and synthesis of combinatorial circuits

•Modelling and synthesis of finite state machine



Prerequisites

Tests

Reports on lab works



CC

Additional Information

Curriculum->SEI->Semester 7

Bibliography

VHDL du langage à la modélisation, R. Airiau J.-M. Bergé, V. Olive J. Rouillard, Presses Polytechniques et Universitaires Romandes

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Université Grenoble Alpes