Phelma Formation 2022

Processor architecture and hardware security - 4PMEAPS3

  • Number of hours

    • Lectures 24.0
    • Projects 0
    • Tutorials 12.0
    • Internship 0
    • Laboratory works 0

    ECTS

    ECTS 4.0

Goal(s)

Three distinct parts have to be distinguished

Part 1 – (Micro)processors, evolution of architectures
Analyze the performance criteria of advanced microprocessor and computer architectures. Understand computing power optimization approaches.

Part 2 – Hardware security (awareness)
Understand security threats related to a physical system implementation (microprocessors, but also ASIC, FPGA … beyond purely software or network threats), evolutions of attacks and related areas, and approaches to evaluate the security level.

Part 3 – Work in groups
Application of approaches explained in part 1 and evaluation of two types of competencies: work in group, in a perspective Research and innovation.

Contact Regis LEVEUGLE

Content(s)

Part 1 – (Micro)processors, evolution of architectures
Notion of performances, evaluation methods
Optimization approaches for computing power (pipeline architectures, types of parallelism, multiprocessor architectures)
Microprocessors: execution models, architectural evolutions (CISC, RISC, superscalar, superpipeline, VLIW, MT, SMT), hazard management techniques – digital synchronous systems, mono-core
Classification and characteristics of memorization elements and memory blocks, memory hierarchy, caches (architectures, management policies), MMU
Macro-parallelism (multi-core architectures)
New paradigm: in memory computation
Links between hardware and software (showed between the lines)

Part 2 – Hardware security (awareness)
Hardware security: general context and evolutions, related areas
Secured circuits: certification, common criteria
Overview of usual hardware attacks
Modelization/Characterization of errors
Other types of attacks and threats
Influence of design style
Protection methods, or counter-measures (possible ways showed between the lines)

Part 3 – Work in groups
Design / optimization (multi-criteria) of an original RISC V processor architecture starting from the basic instruction set



Prerequisites

Part 1 – (Micro)processors, evolution of architectures
Basic architecture of microprocessors (command/operative parts architecture), instruction set, addressing modes ...

Part 2 – Hardware security (awareness)
Digital design

Part 3 – Work in groups
Digital design, part 1 of this course

Test

Session 1: written exam 2h (70% of total grade) and architecture proposal report (30% of total grade)
Session 2: re-taken exam replacing the previous exam grade (oral 30 minutes or written exam 2h depending on the number of re-taken exams), report grade unchanged

N1 = (0.7 E1 + 0.3 report)
N2 = (0.7 E2 + 0.3 report)



Session 1 : examen écrit 2h (70% de la note totale) et rapport de proposition d'architecture (30% de la note totale)
Session 2 : examen de rattrapage remplaçant la note précédente d'examen (oral 30 minutes ou écrit 2h selon le nombre de rattrapages à réaliser), note de rapport inchangée

N1 = (0,7 E1 + 0,3 rapport)
N2 = (0,7 E2 + 0,3 rapport)

Additional Information

Course list
Curriculum->SEI->Semester 7

Bibliography

K01-HEN
J. Hennessy, D. Patterson, Computer architecture: a quantitative approach, Morgan Kaufmann, (2nd edition 1996 and 5th edition 2012)

K01-PAT
D. Patterson, J. Hennessy, Organisation et conception des ordinateurs : l'interface matériel/logiciel, Dunod, 1994 (version française)

K04-PAT
D. Patterson, J. Hennessy, Computer organization and design: the hardware/software interface – RISC-V edition, Morgan Kaufmann, 2018