School of engineering in Physics, Applied Physics, Electronics & Materials
This project focuses on the implementation of signal processing algorithms on targets of different natures: FPGA and GPU. Through these various targets, the aim is to illustrate an approach to algorithm-architecture matching .
Industrial development tools are implemented in this teaching.
The project is divided into two parts :
1) FPGA : Hardware optimal filter edge detection on images in real-time implementation. From the expression z smoothing filters and bypass Deriche and a detector suitable outline, it is proposed to optimize the design of the architecture described in VHDL. The simulation is used to validate the algorithms on a functional level. The aim is to implement the processing on a FPGA development kit connected to a video camera.
2) Processor GPU : optimization of basic algorithms for image processing (rotating, filtering, histogram, Canny-Deriche filter calculation) on a programmable GPU graphics card
Rapport : 100%
 R. Deriche « Fast algorithms for low-level vision », in IEEE transactions on pattern analysis and machine intelligence, vol PAMI-12, no 1, pp 78-87, jan 1990
Didier Demigny, Frederico Garcia Lorca, Lounis Kessal, De l'architecture à l'algorithme. Un exemple : le détecteur de contours de Deriche, in Traitement du Signal - Volume 14 n°6 - special 1997 - pp 615-623
 Jeremie Hamon and al. «FPGA implementation of a real time multi-resolution edge detection video filter », in Proceedings of 8th European Workshop on Microelectronics Education EWME 2010 conference, May 10-12, 2010, Darmstadt, Germany
Date of update June 11, 2015