Number of hours
- Lectures 10.0
- Projects 0
- Tutorials 0
- Internship 0
- Laboratory works 32.0
ECTS
ECTS 3.5
Goal(s)
The course aims to introduce current approaches to the design and validation of hardware / software SoCs architectures (Codesign, Cosimulation, Codevelopment, Exploration and Performance Estimation, etc.).
Contact Andrea BATTISTELLAContent(s)
The course is focused on the following aspects:
- Methodology of SoC design, modeling and specification
- Functional Models
- Transactional Models (TLM)
- Cycle Accurate Models (BCA)
- High Level Synthesis Models
- Software / hardware partitioning / co-design / co-simulation
- SoCs performance analysis (cycles / power)
- Embedded software design (HW parameters to header files, Initialization / Boot code, Device drivers)
The course integrates many labs with the aim of familiarizing students with high level modeling languages ex.SystemC/C++ ?and their application to the SoC design flow. The aspects of functional modeling, TLM, BCA, RTL, HLS, Power, eSW as well as cosimulation will be tackled in the labs sessions.
Prerequisites
Computer architecture, VLSI design
HW and SW programming languages: VHDL and C language
Test
TP and project reports + project oral presentation
50% soutenance+ 50% rapport TP
Additional Information
This course brings 3.0 ECTS to students in Block System on Chip
Course list
Curriculum->SEI->Semester 9
Curriculum->SEOC->Semester 9