VHDL-AMS Bases - 3PMRIVA4
A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail
Number of hours
- Lectures : 2.0
- Tutorials : 2.0
- Laboratory works : 12.0
- Projects : 0
- Internship : 0
- Written tests : 0
ECTS : 1.0
Goals
The objective of this module is to learn the description language VHDL/AMS and to be able to implement it in the frame of a mixed simulation project (including physical description and electronics) of an integrated sensor
Contact Lionel BASTARD
Content 4h of lecture to present the theory of VHDL/AMS description language
12h of practical work using the Cacence framework. This practical work is a project in which VHDL/AMS as well as VHDL and analog electronics are used to simulate a complete system
PrerequisitesNotions of VHDL
Notions of analog electronics design
Tests the grade is given on a written report about the practical work
Additional Information Curriculum->Alternance MT->Semester 6
A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail
Date of update March 6, 2019