Number of hours
- Lectures 2.0
- Projects 0
- Tutorials 2.0
- Internship 0
- Laboratory works 12.0
- Written tests 0
ECTS
ECTS 1.0
Goal(s)
The objective of this module is to learn the description language VHDL/AMS and to be able to implement it in the frame of a mixed simulation project (including physical description and electronics) of an integrated sensor
Contact Lionel BASTARDContent(s)
4h of lecture to present the theory of VHDL/AMS description language
12h of practical work using the Cacence framework. This practical work is a project in which VHDL/AMS as well as VHDL and analog electronics are used to simulate a complete system
Prerequisites
Notions of VHDL
Notions of analog electronics design
Test
the grade is given on a written report about the practical work
Additional Information
Course list
Curriculum->Alternance MT->Semester 6